Noticed this improvement. 
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Looking here those chips range from 1800 EUR to over 10000 EUR per piece.
When you include hardware development costs and parts for entire device, and all the productization stuff, it costs much more than a PC. And it is a single use device, I can write this forum post with the same PC I use for the music playback and processingā¦
The issue here is that such Xeon will have serious clock rate limitations. Likely it cannot get nowhere close to 6.2 GHz i9-14900KS can. With GPU, you only need as many CPU cores as you have output channels. Additional E-cores are nice for running all the lighter stuff.
I donāt think you are comparing apples to apples here.
I am sorry to point out, but the topic is about multichannel DSD1024, and all my comments, are with this subject in mind. There is no PC configuration on this fair planet that can do 16xDSD1024, realtime or not. You can throw in as many nvidia gpus as you like, the DDR bus will suffocate and the cpu will get melted. On the other hand, a 100$ used fpga can do that and its temperature barely hits 50C. I am not developing a commercial product, itās a custom device. But the main point is, that fpga is rock stable, it canāt hang, bsod, lag or anything. The worst nightmare that can be, is a failing PC in a middle of a party or live performance. With fpga that can happen with a chance 1 to million, and not in the favor of the pc.
Anyway, for my custom project I had a goal, to find a multichannel latency free, non usb feeder for 8 DSC2 boards, and I achieved it, I made one myself and upsampling/sdm conversion was a bonus. And frankly, Iām pretty happy with the result, I hardly notice any audible difference, between my build and a commercial DSC2.
My last build, has filter/modulator selection, which are stored in the qspi memory, and can be loaded, injected and executed on the fly, realtime. Modulation rate also can be adjusted realtime. Fpga is not so unflexible as one may think. But an important point is, that is does a job consuming 1-2 watts while a pc does consume over one kilowatt at the same task.
I had a problem, I found a solution, my post was just that about.
Yes there is, not even hard to do. AHM7EC8B is not particularly heavy.
Note that regular modulator like DSD7/ASDM7 is not suitable for DSD1024 for such DAC, the quality will just suffer. It needs a totally different kind of modulator. DSD256 is optimal from a āregularā modulator to such DAC.
Did you try the exact same task (algorithm) on a PC, optimized for a PC hardware?
You are comparing apples to oranges here.
Good that you are happy with your results, but it has nothing to do with HQPlayerās algorithms. So you are comparing more to something like you can find inside DAC chips. Where for example the oversampling filter is not processed to the final output sampling rate, but instead something lower. And then they use something ugly like sample-and-hold (zero order hold) or linear interpolation to go from there. Which is what HQPlayer is designed to replace with better algorithms that Iāve been developing for the past 28 years.
There are many HQPlayer users running 64 million tap filter at 50 MHz sampling rate without issues.
Dual channel DDR on those 14900KS wont deliver, been there, tested that.
My version of DSC2 is far away from what you have from Pavel, hes design has a major flaw in power supply, the ADP7118 per channel, those per register LC resonates at 5khz , dead center of the earās most sensitive region. The original Bom is outdated, current manufacturing versions are much better.
I donāt have any good measuring equipment, this was done with RME ufx iii, DSD512. DSD256 measures almost the same, and DSD1024 only slightly worse. And this was done while feeding DSC2 directly from GPIO of a development board using dupont wires, using bitclock from FPGAs MMCM derived from onboard 200mhz oscillator 
For the record, the EC modulator measures better than pure SDM7 or SDM5. While wenn i measured the DAC using HQPlayer, EC modulators usually measured poorer.
Which filter ? if you are talking about mphase filter family, i probably could buy that. 64 million taps fir filter will give you over 5 minutes of delay, regardless of the hardware, its pure arithmetics you cant subtract.
I also experimented with long fir filters but latency is far beyond that i can accept, and for a multichannel setup mphase filters are not really suited, you cant be sure that all channels are on same phase. So i end up with 9 cascaded 2Ć linear-phase interpolators, 141/127/31/19/15/11/9/9/7 taps, 27-bit coefficients. The modulator runs 49.152 MHz, one quantizer decision per bit clock, not a lower-rate stream repeated. It carries seven explicit integrator states X1ā¦X7 with coefficients A1ā¦A7, 45-bit state arithmetic saturating at Ā±8 FS, single-bit quantiser. NTF has seven zeros ā DC plus 8.1 / 14.8 / 19.1 kHz ā H_inf 1.5, OSR 1229, in-band NTF RMS ā295.7 dB.
This gives me 96khz to 49mhz with sound quality i would buy everyday in UNDER 1ms of latency, internal fpga latency included. I measured latency with REW, ufx iii. REW was sending into two MADI channels, one for the DAC, one for the loopback reference, DAC output into RME analog input ā¦ under 1ms. The filter itself is something like 0.360ms. Right now, there is no hardware architecture available that can beat that. For the record, RME devices have a latency of 0.1582ms, so i would guess they use minimum phase filters. Correction, judging by measurements RME donāt use FIR at all, it looks like they rely on IIR filters.
HQPlayer is a great product, hands down, iāve bought 3 licences and tried everything thatās possible, its an extraordinary package for audiophiles to enjoy quality sound at home. But its not usable in PRO environment. It has nothing to do with HQPlayer itself, but with IBM compatible PC architecture. A complete GPU path is well over 10ms, then we have DDR latency, operating system scheduling, network latency for input and NAA etc etcā¦ you are right, apples!=oranges.
No, a bit over second, since sampling rate is about 50 MHz (DSD1024). And it is a linear phase FIR. So it processes about 50 million output samples per second, with 64 million taps. 1024x conversion ratio.
Not my personal favorite, but it is there.
That is DAC chip category, also in terms of precisionā¦ For example ESS uses 32-bit fixed point coefficients. And I guess you use also fixed point arithmetics. While HQPlayer at minimum uses 64-bit floating point, and when needed 80-, 128- or arbitrary precision floating point.
So a very simple oneā¦ I guess not even dithered?
It is not adaptive one even though you referred to my adaptive modulators.
It is well good up to at least 8 channels, which is what the topic here says. And it is not even heavy loaded, Iāve testedā¦ Two pieces of 32 GB DDR5-6400 CL32.
Iām not talking about Pavelās design, because in my opinion the transformer output spoils it. I instead used 4th order active transient optimized LPF plus cable capacitance compensated output driver stage. As result, the output doesnāt have any overshoot and for example 7 kHz square wave is completely perfect.
Wow, thanks for the tip, why i didnāt come up with the idea of filtering at 49mhz before handing the data for SDM 
, can do same thing on FPGA , 16384 taps will cost me 0.167ms
dithered, left and right channels use their own seeds, generated by two 24-bit LFSRs.I used what i could findā¦ iām not skilled enough to write my own DSP code, and i couldnāt find any commercial grade DSP IP cores available for sale.
it is a matter of taste reallyā¦ i do not listen to the measurements, i listen to the music. My storage room is packed with tens of DACs priced twice or triple more then DSCā¦ yet they are in the storage room ā¦ there is a good point using transformers alsoā¦ the DAC ground is isolated from the amplifier groundā¦ my biggest disappointment was spring 3 kte, i tried to convince myself that its a better DAC, measurements speak for themselves etcā¦ no chance, this analog, vinyl like sound, touches the soul.
i think i know whyā¦ i added 8192 and 16384 taps on my current APOD filter, it gave nothing worth spending resource to ā¦ even without additional taps the filter delivers only 0.00048 dB ripple through 20Khzā¦ nothing measurable or audible, spending resources just for numbers sake smells like a sect cult 
even better, i can derive a higher clock pushing MMCM to run fabric 49,152mhz x4 or x8 and filter at that speed, this gives an opportunity to run 65,536-coefficient, Type-II linear-phase, Kaiser-windowed sinc low-pass polyphase interpolator, 512 phases Ć 128 taps per phase. This allows for 16 channels DSD1024 to have 64k taps each, and those actually did matter, SNR increased by 1.5 db. While Intel CPU is running Ghz speed, isnt it possible there to filter at that speed also ?
But the biggest challenge is making this board to happen.
Yes, very easyā¦ 64-bit floating point precision.
What you are doing sounds quite a bit like SoX.
But a GPU with 24000+ DSP cores can of course process for example convolution with 128 million taps at that rate.
Yes, you are completely right!!! I ponder though, why such modulator is not present in HQPlayerā¦? there are alot of people who use DSC and are happy, this would be gold for them, its not only measurements, the sound improved fantastically. And before you say that there are tons of different DSC designs, the modulator need to adapt only to how 74AHCT595 works, regardless of the other components and layout.
I have completed an extensive test with modulators and measurements and the best measurements iāve got are at DSD1024 not DSD256. 102.5db SNR, 17.7 bits ENOB, with a dynamic range almost 110db. at -6 dBFS. DSD512 and DSD256 measure considerable worse. Adding dither and EC, also measure worse.
Iāve used an āDSC2 awareā interpretation of your AMSDM7 modulator, and this is the best result iāve got. Other regular modulators like ASDM5 or 7 had a hard top of 90db SNR. When i was experimenting with HQPlayer, i never got SNR above 85-86db, regardless of the filter/modulator combo used with a commercial version of DSC2. The best results yet come from a Spartan7 development boardā¦ with pulse stabs etc and an old revision of DSC2 with TI switchers. The black DSC2 version use nexperia and rubycon caps.
This is a real gamechangerā¦ the measurements are getting close to spring 3ā¦ with proper clocks and power, good old DSC2 can put in a fight.
It is, AHMxEC8Bā¦
That particular modulator never measured any better than ASDM family, iirc best measures iāve got were from ASDM5EC-Fast .
I donāt know about your DAC or measurement equipment. How much does you analyzer have stop-band attenuation? So that it doesnāt for example alias ultrasonic noise to mess your audio band measurements.
But what Iāve measured on DSC1, Holo, etc. it is significantly better, both noise and distortion significantly lower. And much better multitone and IMD-vs-level sweep. It is actually competitive with DSD256 which is otherwise the sweet spot with discrete DSD DACs.
I developed it because it actually makes DSD1024 useful.
I respect you point Jussi, its got a lot of sense and my information is somehow vague. What i wanted to say is that ANY modulator can perform much better with DSC2 if its quantizer operate on a complete DSC2 frame instead of producing an unrestricted bit every 49.152 MHz cycle
AHM5/AHM7 or any other modulator loop at 3.072 MHz ā multibit frame level ā EC/frame residual ā centered N16 word ā serialize at 49.152 MHz, for each frame i choose level m = ā4ā¦+4 then number of ones k = 2 Ć (m + 4)
These palindromic words have a single centered run of ones, giving no more than two data transitions per 16-bit frame. Expected transition activity is approximately 12.5%, versus the ordinary raw AHM schedulerās 52ā64%
Less switching = less noise.
I understand your approach in willing to support only mass production retail DACs, it is impossible to keep on countless diy projects, but in the case of DSC, regardless of the fork, they all use same shifting registers.
The filtering can be done at any rate, right now iām experimenting with FIR filters running at 49.152 x8, that gives me 128k taps on least power consuming Xilinx FPGA and measure very well using this DSC2 adaptation algorithm.