Can someone explain what’s happening here? i.e., is the equalization now being done WITHOUT converting to PCM, or is the conversion still happening, but just hidden - either by design or by accident?
We released support for native DSD processing in mid-2017, IIRC. The signal paths are correctly reflecting what is going on–there is no decimation to PCM involved.
The DSD64/128 signal paths from @Katun look wrong to me–it shouldn’t be dipping down to 352.8kHz there (@vova, please track this).
No, we don’t have logic like that. It feels like a mis-handled case in the SRC planner to me. Normally in PCM->DSD upsampling cases, DSP is inserted at 352kHz, before taking the “big” upsampling step to DSD. It feels like that logic is being mis-applied to DSD source material, causing an unnecessary (and inefficient) down->process->up.