What Ted Smith is referring to is “phase noise”. If you think of a SPDIF signal in the time domain, what he means is that the leading edge of the transition drifts around a bit, so it comes a little later or a little sooner than it should. In the frequency domain this shows up as phase shifts.
When I say “low frequency drift” I mean that this meandering back and forth occurs slowly compared to the SPDIF signal frequency, which is in the MHz range. There can be many sources of this type of phase noise: ground plane noise, power supply noise that is not filtered enough, electromechanical feedback, etc.
As I explained before, if you’re playing a 5KHz digital sine wave and you have phase noise at 1KHz, it will introduce bands are 4KHz and 6KHz.
In an external clock, or a well designed internal clock, designers try to minimize all of these factors. It is easier to do when you can design the power supply, casing, dampening, and ground plane all on its own and tailored to the clock.
In the dCS ecosystem, given the digital signal transmission is over SPDIF/AES, a design with a central master clock orchestrating the entire system timing is the right thing to do.
Of course this is not the only possible design.
