This could be potentially useful, if the firmware is flexible enough. But doesn’t seem like they are very interested in this. And in this shape, this is just a feature list without any actual specifications.
If they can increase sample rates, why not just keep increasing them?
Because the hardware cannot do it. These clocks are generated from the CPU clock based on certain dividers. And the logic hardware there has some limitations what it can keep up with,
Do we already know what the rpi 5 can do in this area?
I don’t have specific information, but I suspect that the I2S IP block is the same as before…
I cannot find datasheet for the BCM2712 SoC…
Anything useful in this? Or this is all about that other chip.
Not much, it has 8 channels worth of I2S (four inputs and four outputs, so 8 channels in/ou), but that’s all.
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