Any one knows? I measured the LR and Data signals coming from a rpi3 with Ropieee and noticed that the last 16 or 8 bits depending on track format, were padded with “ones” in stead of the expected zeroes…
On normal I2S DACs no issue, as it is lsb stuff
The PI is feeding an Ian Canad FiFoPi Q2 to be complete…
But on a DAC I have here which likes left justified format, I am getting now always a one as MSB, causing crazy cut in half signals….
Update, it seems the Data signal is being inverted by Ropieee. That would result in the “ones” where “zeroes” are expected.
I simulated some I2S signal on my Audio Analyzer and by hitting the Data invert Button, I got exactly the same looking I2S signals, hence my suspicion.
Of course only the one who coded Ropieee will be able to tell if the data signal comes out of the GPIO inverted or not
Hope someone will shine a light on this
Below is a scope screenshot from the I2S signals.
Thanks
Doede
Which HAT do you have configured in RoPieee?
Hi Harry,
The one at the bottom of the list, the RPI generic I2S it is called I believe….
can you try with the ‘HifiBerry DAC’?
Still inverted. Also, data shifted to the right, this was not generic I2S anymore. Looked more like right-justified plus one extra clock cycle shifted further…
this is how it should look like (except for logic level Volts)
Harry, have you been able to reproduce this at your RPI with Ropieee at your Lab ?
No I cannot. As this is standard Linux kernel functionality I also cannot imagine that this is fundamentally broken.
