My mistake of not actually answering the question… Reason why DACs do this cascade of filters with reduced taps per cascade is required processing resources. It saves DSP resources, compared to single step.
Overall, when a DAC chip is designed it needs to fit some required price point and utilize one of the standard master clock frequencies. Other constraints are power consumption and related requirement of not having a heat sink or active cooling. Also amount of on-chip RAM is limited. Then the designers try to fit things into the chip within the given constraints.
Also proximity of analog / mixed signal stage imposes it’s own constraints on what can be done without sacrificing SNR.