OK. The following argument applies to USB connected DACs since that is the setup that @David_Snyder originally described. SPDIF (and similar source clocked interfaces) connected DACs will often behave somewhat differently. Whether these differences are audible is again up for debate. I have no opinion never having used an SPDIF connected DAC.
But, with USB, the time domain aspect is managed solely by the DAC. With UAC2 and asynchronous audio, the USB host clocks and the DAC sample clock are not directly tied together. The USB host sends packets at regular intervals. The sample rate within the packet is much higher than that required by the DAC and so these samples are placed in a buffer so that the USB sample rate and the DAC sample rate can be decoupled. The number of samples in those packets is adjusted (by means of a feedback channel on the USB bus in the reverse direction) to maintain the correct average sample rate demanded by the DAC and determined by the DACs sample clock. The nominal number of samples in the packet is determined by comparing the packet frequency (either 1000 or 8000 per second for USB isochronous channels) with the sample rate. The average number of samples per packet is not likely to be an integer - at least for PCM.
For example, 44.1kS/s divided by 1000 packets per second means that, on average, 44.1 samples will need to be sent in each packet. Since it is not possible to send .1 samples, the nominal number of samples would, I imagine, be set to 44 which would result in a shortfall in samples over time. Thus a feedback channel is used to signal to the USB host that, occasionally (1 in 10), a packet with 45 samples is required. (Note: the number of samples in a packet is always nominal, nominal + 1 or nominal - 1)
The use of this feedback channel can also be used to accommodate small relative errors in the clocks on the USB host and the sample clock on the DAC. If the DAC sample clock is slightly slower than the USB host expects, the feedback channel will be used to adjust the average sample rate by reducing the number of nominal +1 packets sent (or sending some nominal - 1 packets). Similarly, if the DAC sample clock is slightly faster than the USB host expects, the number of nominal + 1 packets is increased (or the number of nominal - 1 packets is decreased). In this way the number of samples in the buffer can be managed so that buffer overruns and buffer underruns never occur and there is always a sample available for the DAC to use when its sample clock demands a sample be presented to the digital to analogue converter. Thus the time domain aspects of the DAC are controlled solely by the DAC and are independent of the USB host or the USB bus itself.
Thus, if you are suggesting that a time domain difference is observed, I would have to ask how the use of diretta can affect the sample clock in a USB connected DAC - even when the timing of packets (and their average size) over USB is not changed. diretta manages the flow of data over Ethernet to the diretta target but it does nothing to alter the traffic from the diretta target to the DAC over USB.